The present invention relates, in general, to the field of integrated circuit (xe2x80x9cICxe2x80x9d or xe2x80x9cchipxe2x80x9d) memory devices. More particularly, the present invention relates to an improvement in a memory design to account for delays in the reading and writing paths within the integrated circuit.
A given design for an integrated circuit memory such as a DRAM usually has a set design for a xe2x80x9cwrite data pathxe2x80x9d that transfers input data on I/O pins into a memory array as is known in the art. The write data path may include several stages of latches and multiplexer points on its path from the data I/O pins to the memory array. The write data is sorted and moved about the chip in such a fashion as to coincide with the corresponding correct address and clock information.
However, every bit of write data in the path usually sees the same configuration of circuits. In large die, especially those with address/clock and data information coming from opposite points in the chip, the resulting time skew leads to errors and a resultant severe limitation in the maximum operating frequency.
Referring now to FIG. 1, a conceptual block diagram of the address 12 and data 14 paths of an integrated memory chip 10 are shown. Delays within the integrated circuit due to transmission delays through integrated transistors and logic gates can adversely affect performance. For large die with non-symmetrical address/data paths, problems can particularly occur during writing as is explained in further detail below.
For reading, the fastest points in the chip for address path A has the slowest data, while the slowest addresses have the fastest data at point C. Thus, the total delay for address and read data remains relatively constant. The memory design for the read mode can proceed in a straightforward manner.
For writing, however, the fastest address area of the chip at point A receives the slowest data. In turn, the slowest address area at point C also has the fastest data. The changes in the internal delays depending upon chip location in the write mode is thus very challenging for the memory designer.
What is desired is a circuit and method for counter-acting or offsetting the location-specific timing delays inside the memory chip in order to reduce timing errors and improve overall performance.
According to the present invention, particularly disclosed herein is a circuit and method for improving the performance of an integrated circuit by adding an extra latch into the write data path. The added latch is programmable such that it either is disabled (allowing the transparent flow of data), or enabled (data flow is inhibited by extra clock). In areas of the chip where the address/control information is fast, but the data is slow, the latch is disabled to allow the data to flow as fast as possible. In areas of the chip where the address/control information is slow, but the data is fast, the latch is enabled such that data cannot flow freely and must be gated by clock information. The control of the latch circuit with prevents corruption of the data for a given address (Y) by ensuring data for the next address (Y+1) does not arrive too soon.
The design of the write path for the entire memory chip remains unaffected except for the extra write path latch circuitry. The extra write path latch circuits are programmed with a static enable or disable command for various locations in the chip depending upon which timing case applies. In this way a contour can be drawn on the chip, dividing the chip into two parts. On one side of the contour, the write path latch circuit is enabled. On the other side of the contour, the write path latch circuit is disabled. The contour is found through empirical studies of chip performance or computer simulations.
The memory chip therefore has two sections in which the write path timing is handled differently. In one section of the chip, the timing is unaltered. In another section of the chip, an extra delay or xe2x80x9chold-offxe2x80x9d is provided under a clock control signal to allow the data and address/clock signals to be properly aligned and to eliminate undesirable time skewing. In this way, the write path timing is selectively optimized according to chip location, thereby minimizing timing skew errors and increasing the maximum frequency and overall performance.